1. Field of the Invention
This invention relates to wiring layers having structure suited for use as electrode wiring in a semiconductor device having a highly integrated structure, and to a method of manufacturing such wiring layers.
2. Description of the Background Art
In the field of semiconductor devices, element structures are becoming increasingly miniaturized and integrated to meet the demands for greater capacity and performance. A semiconductor device includes numerous electrode layers and wiring layers, and these conductive layers are patterned to fine structures to meet the demand for a greater scale of integration. The demand for miniaturization of wiring layers has led to a reduction in conductive area of the wiring layers and a reduction in contact regions with certain other conductive regions. Consequently, various measures have been taken to reduce or suppress an increased wiring resistance resulting therefrom.
One such measure is use of a highly conductive material as a wiring material. There is, for example, a wiring structure having a refractory metal silicide layer formed on a surface of a polycrystalline silicon layer. Such a wiring structure will be described hereinafter. The description will be made in relation to a memory cell structure of a DRAM as a specific example in which such a wiring structure is employed.
FIG. 22 is a sectional view of a memory cell structure of a conventional DRAM. A memory cell forms a minimum unit for storing unit information, and is made up of one transfer gate transistor 3 and one capacitor 10. This DRAM has a plurality of memory cells arranged in matrix form on a substrate to provide a large capacity storage region. A memory cell array forming the storage region includes a plurality of word lines 4 extending parallel to one another, and a plurality of bit lines 15 extending perpendicular thereto. Each memory cell is isolated on a surface of a silicon substrate 1 by a field oxide layer 2.
The transfer gate transistor 3 includes a gate electrode 4 formed of part of a word line, a pair of impurity regions 6, and a gate insulating layer 5 interposed between the silicon substrate 1 and gate electrode 4. The capacitor 10 has a multi-layer structure including a lower electrode 11, a dielectric layer 12 and an upper electrode 13. The gate electrode (word line) 4 is surrounded by an insulating layer 7.
There is a strong demand particularly for increases in the capacity of such memory cells of DRAMs, and miniaturization of the element structure is an important technical problem to be solved for meeting this demand. The demand for miniaturization of the structure has led to a reduced gate length of the transfer gate transistor 3 on the order of submicrons. Consequently, it is inevitable for the gate electrode 4 to have a reduced sectional area. In the structure shown in FIG. 22, therefore, the gate electrode (word line) 4 has a layered structure including a polycrystalline silicon layer 4a used widely heretofore, and a titanium-silicide layer 4b formed in a self-aligning manner on an upper surface and lateral surfaces of the silicon layer 4a. The titanium-silicide layer 4b has a higher conductivity than the polycrystalline silicon layer 4a. Thus, conductivity is improved with the illustrated electrode 4 compared with a gate electrode formed of polycrystalline silicon and having an equal sectional area.
A process of manufacturing the above memory cells will be described next. FIGS. 23 through 29 are sectional views illustrating a conventional memory cell manufacturing process.
Referring to FIG. 23 first, the field oxide layer 2 is formed in a predetermined region on a surface of the silicon substrate 1, using the LOCOS (Local Oxidation of Silicon) method.
Referring to FIG. 24 next, the gate insulating layer 5 and polycrystalline silicon layer are formed successively on the surface of silicon substrate 1. The polycrystalline silicon layer is patterned to a predetermined shape to form first conductive layers 4a of the gate electrodes (word lines).
Referring to FIG. 25, a titanium layer 25 is formed on the silicon substrate by the sputtering method.
Referring to FIG. 26, a heat treatment is effected to produce a silicide reaction in regions of the titanium layer 25 contacting the surfaces of polycrystalline silicon layers (first conductive portions) 4a, thereby forming the titanium silicide layers 4b. This provides the second conductive portion of each gate electrode 4. Thereafter the unreacted parts of the titanium layer 25 are removed.
Referring to FIG. 27, impurities are ion-implanted into the silicon substrate 1, using the gate electrode 4 as a mask, to form the pair of source/drain regions 6. Thereafter an insulating layer 70 such as of oxide film is placed over the entire surface.
Referring to FIG. 28, a resist pattern 20 having a predetermined opening pattern is formed by photolithography and etching. This resist pattern 20 is used as a mask to etch away the insulating layer 70, thereby forming an opening 21 reaching one of the source/drain regions 6. One problem arises from this process. It is an error occurring in mask alignment when forming the resist pattern 20. A solid line in FIG. 28 indicates a desired shape of the resist pattern 20 having the opening 21. However, the error in alignment between the silicon substrate 1 and resist mask for forming the resist pattern 20 is inevitable. As a consequence, the opening 21 of the resist pattern 20 may be deviated. Especially, with development of the large scale integration technique, the source/drain region 6 now has a reduced range of transverse diffusion on the order of submicrons. This results in an increased chance of a deviation 22 occurring in the mask alignment. When the deviated resist pattern 20 is used as a mask in etching the insulating layer 70, the part of insulating layer 70b covering an upper part or lateral surface of the gate electrode 4 is etched away, thereby exposing a surface of the second conductive portion 4b of the gate electrode 4.
Referring to FIG. 29, after covering the gate electrodes 4 with the insulating layer 7 in the above process, the lower electrode of capacitor 10 is formed in a way to connect with the source/drain region 6. Thereafter the capacitor 10 is completed by forming the dielectric layer 12 and upper electrode 13. When the mask deviation occurs with the resist pattern 20 in the foregoing process to expose part of the second conductive portion 4b of gate electrode 4, a short-circuiting situation arises from contact between the lower electrode 11 of capacitor 10 and the second conductive portion 4b of gate electrode 4.
As exemplified by the word lines of the DRAM, the conventional layered wiring structure of the polycrystalline silicon layer and silicide layer has the following disadvantage. When forming a conductive layer over the layered wiring with an insulating layer in between, the conductive layer covering the wiring is patterned using a mask process such as photolithography. Part of the insulating layer completely covering the wiring may be etched as a result of a mask alignment error, thereby producing defective coating. And the defect in the insulation coating of the wiring causes a defect in the insulation with the conductive layer.